Digital word generators are well known in the prior art for generating a train of digital data. Referring to FIG. 1, a memory 403 stores desired output data and sequentially outputs the data in response to an address indicated by the address counter 401. The address selection is synchronized with a clock signal f.sub.CLK at an interval between a preset first address and a preset last address. Therefore, it follows that a train of corresponding data written between the first and last addresses of the memory are output from memory 403.
An address comparator 402 determines whether the address generated by the address counter 401 has reached the last address. Several data train output modes may be selected. When the address generated by the address counter is the last address, the output data train is terminated. Alternatively, the data train between the first and last addresses may be repeated by returning to the first address once again. Still another data train mode may repeat the data a predetermined number of times using a separate counter to count out each time the first counter reaches the last address. Furthermore, a different data train may be generated by rewriting the first and last addresses when a given number of repetitions are finished. Generating a different data train output may also be provided by a conditional mode causing the first and last addresses to be rewritten when the condition is satisfied. However, it is impossible to attain higher data rates due to a limited memory operating speed.
To cope with this drawback, the system depicted in FIG. 2 generates a data train at a higher speed than the memory operating speed. A n-divider 505 (n is a natural number) divides a frequency of the clock signal f.sub.CLK by n, and the n-divided clock signal is applied to the address counter 401. Addresses generated by the address counter 401 serve to specify addresses of a memory group, i.e., a memory 501 consisting of n-memory banks arranged in parallel. It follows that n-memory banks are simultaneously specified per address. Outputs of the respective banks are latched by their corresponding latches of a latch 502. Accordingly, latch 502 comprises n storage latches and provides output data at a rate f.sub.CLK /n. The n latches are sequentially selected in time series by a multiplexer 503 triggering the data stored in the selected latch to be output. The data train output, therefore, is n-times higher than memory speed.
The data train can be generated at a much higher speed than the memory speed as n increases. However, since n is fixed, the number of data must be a multiple of n. Based on the prior art, if the number of data is not a multiple of n, the number of data is changed into a multiple by adding extra or insignificant data thereto. However, if the extra data are not added due to a restriction in practicable memory capacity, or because it creates a futility in terms of memory utilization by writing the data trains for several cycles, the data limitation to multiples of n becomes problematic.
Furthermore, the data train output sequence cannot be varied at the higher rate f.sub.CLK /n by the system shown in FIG. 2. Changes in the desired sequence may occur only by changing the first and last addresses in memory 501, and is, therefore, limited to the operation rate of the memory 501. Even if a conditional mode is used to change the data sequence, the desired change cannot take place until the latch 502 is triggered and new data is read from memory 501 into the latch 502. Therefore, an extra waiting time and a variable waiting time are required between the time a condition is met and the actual change in output data.